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W49V002FA 256K x 8 CMOS FLASH MEMORY WITH FWH INTERFACE
GENERAL DESCRIPTION
The W49V002FA is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K x 8 bits. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49V002FA results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers.
FEATURES
*
Single 3.3-volt operations: - 3.3-volt Read - 3.3-volt Erase - 3.3-volt Program
* * *
Two 8K bytes Parameter Blocks Four main memory blocks (with 32K bytes, 64K bytes, 64K bytes, 64K bytes each) Low power consumption - Active current: 40 mA (typ. for FWH) Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling
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Fast program operation: - Byte-by-byte programming: 50 S (typ.) Fast erase operation: 150 mS (typ.) Fast read access time: Tkq 11 nS Endurance: 10K cycles (typ.) Twenty-year data retention Hardware data protection - #TBL & #WP serve as hardware protection One 16K bytes Boot Block with lockout protection
* *
* * * * * *
* * *
Latched address and data TTL compatible I/O Available packages: 32L PLCC, 32L STSOP
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
PIN CONFIGURATIONS BLOCK DIAGRAM
#WP #TBL CLK FWH[3:0] FWH4 IC
#RESET
BOOT BLOCK 16K BYTES Interface PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES MAIN MEMORY BLOCK1 32K BYTES MAIN MEMORY BLOCK2 64K BYTES MAIN MEMORY BLOCK3 64K BYTES MAIN MEMORY BLOCK4 64K BYTES
3FFFF 3C000 3BFFF 3A000 39FFF 38000 37FFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000
A 8 ^ F G P I 2 v 4 A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) A3(ID3) A2(ID2) A1(ID1) A0(ID0) DQ0(FWH0) 5 6 7 8 9 10 11 12 13
A 9 ^ F G P I 3 v 3
# R E S V END TCD 2
R # C ^ C L K v
A 1 0 ^ F G P I 4 v
#INIT
R/#C A[10:0] DQ[7:0] #OE
29 28 27 IC GND NC GND VDD #OE(#INIT) #WE(FWH4) NC DQ7(RSV)
Programmer Interface
1 32 31 30
#WE
32L PLCC
26 25 24 23 22 21
PIN DESCRIPTION
SYM. IC #RESET #INIT #TBL #WP CLK FGPI[4:0] ID[3:0] INTERFACE PGM * * FWH * * * * * * * * PIN NAME Interface Mode Selection Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs Identification Inputs They Are Internal Pull Down to VSS Address/Data Inputs FWH Cycle Initial Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable Power Supply Ground Reserved Pins No Connection
14 15 16 17 18 19 20 D Q 1 ^ F W H 1 v DGDD QN QQ 2D34 ^ ^^ F FR W WS H HV 2 3v v v D Q 5 ^ R S V v D Q 6 ^ R S V v
NC NC NC GND IC A10(FGPI4) R/#C(CLK) VDD NC #RESET A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32L TSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
#OE(#INIT) #WE(FWH4) NC DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) DQ3(FWH3) GND DQ2(FWH2) DQ1(FWH1) DQ0(FWH0) A0(ID0) A1(ID1) A2(ID2) A3(ID3)
FWH[3:0] FWH4 R/#C A[10:0] DQ[7:0] #OE #WE VDD GND RSV NC
* * * * * * * * * * *
* * * *
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W49V002FA
FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, the other is FWH interface mode. The IC pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH Interface Specification. Through the FWH[3:0] to communicate with the system chipset .
Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE (#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition for further details.
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Sector Erase Operation
The seven sectors, one boot block and two parameter memory and four main blocks, can be erased individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Program Operation
The W49V002FA is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (100 S max. TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. One is software command sequences method; the other is hardware method. 16K-byte in the top location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes of the memory with the address range from 3C000(hex) to 3FFFF(hex). Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set, the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. Besides the software method, there is a hardware method to protect the top boot block and other sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will override the software method setting. That is, if #TBL is at low state, then top boot block cannot be programmed/erased no matter how the software boot block lock setting. Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The enable of this pin will override the #TBL setting. That is, the top boot block cannot be programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting.
Hardware Data Protection
The integrity of the data stored in the W49V002FA is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 1.5V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49V002FA includes a data polling feature to indicate the end of a program or erase cycle. When the W49V002FA is in the internal program or erase cycle, any attempts to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and when erase cycle has been completed it becomes logical "1" or true data.
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W49V002FA
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49V002FA provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.
General Purpose Inputs Register
This register reads the FGPI[4:0] pins on the W49V002FA.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. BIT 7-5 4 3 2 1 0 FUNCTION Reserved Read FGPI4 pin status Read FGPI3 pin status Read FGPI2 pin status Read FGPI1 pin status Read FGPI0 pin status
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software operation. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 32(hex)." The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table). As for FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC, 0001(hex) can output the device code 32(hex).
TABLE OF OPERATING MODES
Operating Mode Selection - Programmer Mode
(VHH = 12V 5%)
MODE
PINS
#OE
Read Write Standby Write Inhibit Output Disable VIL VIH X VIL X VIH
#WE
VIH VIL X X VIH X
#RESET
VIH VIH VIL VIH VIH VIH
ADDRESS AIN AIN X X X X Dout Din High Z
DQ.
High Z/DOUT High Z/DOUT High Z
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Operating Mode Selection - FWH Mode
Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle Definition".
TABLE OF COMMAND DEFINITION
COMMAND DESCRIPTION Read Chip Erase Sector Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit
(1)
NO. OF Cycles 1 6 6 4 6 3 3 1
1ST CYCLE Addr. Data AIN DOUT
2ND CYCLE Addr. Data
3RD CYCLE Addr. Data
4TH CYCLE Addr. Data
5TH CYCLE Addr. Data
6TH CYCLE Addr. Data
5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0
2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55
5555 80 5555 80 5555 A0 5555 80 5555 90 5555 F0
5555 AA 5555 AA AIN DIN
2AAA 55 2AAA 55
5555 10 SA 30
5555 AA
2AAA 55
5555 40
Product ID Exit (1)
Notes: 1. The cycle means the write command cycle not the FWH clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11] 3. Address Format: A14-A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector Address SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 38000h to 39FFFh for Parameter Block2 SA = 30000h to 37FFFh for Main Memory Block1 SA = 2XXXXh for Main Memory Block2 SA = 1XXXXh for Main Memory Block3 SA = 0XXXXh for Main Memory Block4
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W49V002FA
FWH CYCLE DEFINITION
FIELD START IDSEL MSIZE TAR ADDR NO. OF CLOCKS 1 1 1 2 7 DESCRIPTION "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH Memory Write cycle. This one clock field indicates which FWH component is being selected. Memory Size. There is always show "0000b" for single byte access. Turned Around Time Address Phase for Memory Cycle. FWH supports the 28 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[27:24] on FWH[3:0] first , and Address[3:0] on FWH[3:0] last.) Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then DQ[7:4] on FWH[3:0] last.)
SYNC
N
DATA
2
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Embedded Programming Algorithm
Start
Write Program Command Sequence (see below)
#Data Polling/ Toggle bit
Pause TBP
No Increment Address Last Address ? Yes Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
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W49V002FA
Embedded Erase Algorithm
Start
Write Erase Command Sequence (see below)
#Data Polling or Toggle BitSuccessfully Completed
Pause T EC /TSEC
Erasure Completed
Chip Erase Command Sequence (Address/Command): 5555H/AAH
Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any sector group address during chip erase
Read Byte (DQ0 - DQ7) Address = VA
No
DQ7 = Data ? Yes Pass
Embedded Toggle Bit Algorithm
Start
Read Byte (DQ0 - DQ7) Address = Don't Care
Yes DQ6 = Toggle ? No Pass
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W49V002FA
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Product
Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit(6)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 00000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 00001 data = 32 (Hex)
(2)
Load data F0 to address 5555
Pause 10 S
Read address = 00002 DQ0 of data outputs = 1/0
(4)
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7 - DQ0 (Hex); Address Format: A14 - A0 (Hex) (2) A1 - A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout Feature Set Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 80 to address 5555
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 40 to address 5555
Pause TBP
Exit
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W49V002FA
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 nS) on Any Pin to Ground Potential RATING -0.5 to +4.1 0 to +70 -65 to +150 -0.5 to VDD +0.5 -1.0 to VDD +0.5 UNIT V C C V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Programmer interface Mode DC Operating Characteristics
(VDD = 3.3V 5%, VGND= 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS MIN. TYP. MAX. 30 10 10 0.8 VDD +0.5 0.45 -
UNIT
Power Supply Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
ICC ILI ILO VIL VIH VOL
In Read or Write mode, all DQs open Address inputs = 3.0V/0V, at f = 3 MHz VIN = GND to VDD VOUT = GND to VDD IOL = 2.1 mA
-0.3 2.0 2.4
20 -
mA A A V V V V
VOH IOH = -0.1mA
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
FWH interface Mode DC Operating Characteristics
(VDD = 3.3V 5 %, VGND = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS MIN.
LIMITS TYP. 40 20 MAX. 60 100
UNIT
Power Supply Current Standby Current
ICC
All Iout = 0A, CLK = 33 MHz, in FWH mode operation.
-
mA A
ISB1 FWH4 = 0.9 VDD, CLK = 33 MHz, all inputs = 0.9 VDD/ 0.1 VDD, no internal operation
Standby Current
ISB2 FWH4 = 0.1 VDD, CLK = 33 MHz, all inputs = 0.9 VDD/ 0.1 VDD, no internal operation
-
3
10
mA
Input Low Voltage Input High Voltage Input Low Voltage for #INIT Input High Voltage for #INIT Output Low Voltage Output High Voltage
VIL VIH VILI VIHI VOL IOL = 1.5 mA
-
-0.5 0.5 VDD -0.5V 1.35V 0.9 VDD
-
0.3 VDD VDD +0.5 0.2 VDD VDD +0.5 0.1 VDD -
V V V V V V
VOH IOH = -0.5 mA
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER I/O Pin Capacitance Input Capacitance
SYMBOL CI/O CIN
CONDITIONS VI/O = 0V VIN = 0V
MAX. 12 6
UNIT pF pF
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W49V002FA
PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 0.9 VDD < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF CONDITIONS
AC Test Load and Waveform
+3.3V
1.8K
DOUT
Input
30 pF (Including Jig and Scope) 0.9V DD 1.3K 0V Test Point 1.5V
Output
1.5V
Test Point
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Programmer Interface Mode AC Characteristics, continued
AC Characteristics
Read Cycle Timing Parameters
(VDD = 3.3V 5%, VGND = 0V, TA = 0 to 70 C)
PARAMETER Read Cycle Time Row/Column Address Set Up Time Row/Column Address Hold Time Address Access Time Output Enable Access Time #OE Low to Active Output #OE High to High-Z Output Output Hold from Address Change
SYMBOL TRC TAS TAH TAA TOE TOLZ TOHZ TOH
W49V002FA MIN. 300 50 50 0 0 MAX. 200 100 50 -
UNIT nS nS nS nS nS nS nS nS
Write Cycle Timing Parameters
PARAMETER Reset Time Address Setup Time Address Hold Time R/#C to Write Enable High Time #WE Pulse Width #WE High Width Data Setup Time Data Hold Time #OE Hold Time Byte programming Time Erase Cycle Time SYMBOL TRST TAS TAH TCWH TWP TWPH TDS TDH TOEH TBP TEC MIN. 1 50 50 50 100 100 50 50 0 TYP. 50 0.15 MAX. 100 0.2 UNIT S nS nS nS nS nS nS nS nS S S
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
PARAMETER #OE to Data Polling Output Delay #OE to Toggle Bit Output Delay SYMBOL TOEP TOET W49V002FA MIN. MAX. 40 40 nS nS UNIT
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W49V002FA
TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
Read Cycle Timing Diagram
#RESET TRST TRC Column Address TAS R/#C VIH #WE TAA #OE TOH TOE TOLZ High-Z DQ[7:0] Data Valid High-Z TOHZ TAH Row Address TAS TAH Column Address Row Address
A[10:0]
Write Cycle Timing Diagram
TRST #RESET
A[10:0]
Column Address TAS TAH
Row Address TAS TAH
R/#C TCWH #OE TWP #WE TDS DQ[7:0] Data Valid TDH TWPH TOEH
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Timing Waveforms for Programmer Interface Mode, continued
Program Cycle Timing Diagram
Byte Program Cycle A[10:0] (Internal A[17:0]) DQ[7:0] 5555 AA 2AAA 55 5555 A0
Programmed Address
Data-In
R/#C
#OE TWPH #WE TWP TBP
Byte 0
Byte 1
Byte 2
Byte 3
Internal Write Start
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11].
#DATA Polling Timing Diagram
A[10:0] (Internal A[17:0]) R/#C #WE An An An An
#OE TOEP DQ7 X X TBP or TEC X X
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W49V002FA
Timing Waveforms for Programmer Interface Mode, continued
Toggle Bit Timing Diagram
A[10:0] R/#C #WE
#OE TOET DQ6 TBP or TEC
Boot Block Lockout Enable Timing Diagram
Six-byte code for 3.3V-only software chip erase A[10:0] (Internal A[17:0]) DQ[7:0] 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
R/#C
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TWC
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11].
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Timing Diagram
Six-byte code for 3.3V-only software chip erase A[10:0] (Internal A[17:0]) 5555 2AAA 5555 5555 2AAA 5555
DQ[7:0]
AA
55
80
AA
55
10
R/#C
#OE TWP #WE SB0 TWPH SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts TEC
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11].
Sector Erase Timing Diagram
Six-byte code for 3.3V-only software sector erase A[10:0] (Internal A[17:0]) DQ[7:0] R/#C 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TEC
Internal Erase starts
Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. SA = Sector Address, Please ref. to the "Table of Command Definition"
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W49V002FA
FWH INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Slew Rate Input/Output Timing Level Output Load 0.6 VDD to 0.2 VDD 1 V/nS 0.4 VDD / 0.4 VDD 1 TTL Gate and CL = 10 pF CONDITIONS
AC Test Load and Waveform
DOUT
DOUT
10 pF
Input
25 10 pF 25 V DD 0.6V DD 0.4V DD 0.2VDD Test Point
Output
0.4V DD
Test Point
Test when output from low to high
Test when output from high to low
Read/Write Cycle Timing Parameters
(VDD = 3.3V 5%, VGND = 0V, TA = 0 to 70 C)
PARAMETER Clock Cycle Time Input Set Up Time Input Hold Time Clock to Data Valid
SYMBOL TCYC TSU THD TKQ 30 7 0 -
W49V002FA MIN. MAX. 11
UNIT nS nS nS nS
Reset Timing Parameters
PARAMETER VDD stable to Reset Active Clock Stable to Reset Active Reset Pulse Width Reset Active to Output Float Reset Inactive to Input Active SYM. TPRST TKRST TRSTP TRSTF TRST MIN. 1 100 100 1 TYP. MAX. 50 UNIT mS S nS nS S
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition.
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Publication Release Date: February 19, 2002 Revision A2
W49V002FA
TIMING WAVEFORMS FOR FWH INTERFACE MODE
Read Cycle Timing Diagram
TCYC
CLK
#RESET
TSU THD
FWH4 Start FWH Read FWH[3:0]
TSU THD
IDSEL
TKQ
M Size
Address XXXXb
XA[22]XXb XXA[17:16]
TAR 1111b
Sync
Data D[3:0] D[7:4] TAR
Next Start
0000b
1101b 0000b
A[15:12] A[11:8]
A[7:4]
A[3:0]
0000b]
Tri-State 0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock
Note: When A22 = high, the host will read the BIOS code from the FWH device. While A22 = low, the host will read the GPI (Add = FFBC0100) or Product ID (Add = FFBC0000/FFBC0001) from the FWH device
Write Cycle Timing Diagram
TCYC
CLK
#RESET
FWH4
Start FWH Write
TSU THD
IDSEL
Address XXXXb XXXXb
XXA[17:16]b A[15:12]
M Size
Data D[3:0] D[7:4]
TAR 1111b Tri-State
Sync 0000b 1 Clock TAR
Next Start 0000b 1 Clock
FWH[3:0]
1110b 0000b
A[11:8]
A[7:4]
A[3:0]
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
Load Data in 2 Clocks
2 Clocks
- 22 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Program Cycle Timing Diagram
CLK
#RESET
FWH4 Start next command Tri-State
1st Start FWH[3:0 ] 1110b
IDSEL
Address
XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b
M Size 0000b 1010b
Data
1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command Tri-State
2nd Start FWH[3:0 ] 1110b
IDSEL
Address
XXXXb XXXXb XXXXb X010b 1010b 1010b 1010b
M Size 0000b 0101b
Data
0101b
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command Tri-State
3rd Start FWH[3:0 ] 1110b
IDSEL
Address
XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b
M Size 0000b
Data
0000b 1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "A0" in 2 Clocks
2 Clocks
2 Clocks
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
Internal program start 4th Start
IDSEL
Address
XXXXb XXXXb
XXA[17:16]b
M Size A[11:8] A[7:4] A[3:0] 0000b D[3:0]
Data
D[7:4]
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b Tri-State Internal program start
FWH[3:0 ]
1110b
0000b
A[15:12]
1 Clock 1 Clock
Load Ain in 7 Clocks
Load Din in 2 Clocks
2 Clocks
2 Clocks
Write the 4th command(target location to be programmed) to the device in FWH mode.
- 23 -
Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
#DATA Polling Timing Diagram
CLK
#RESET
FWH4
Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb
XXA[17:16]b
Address
An[15:12] An[11:8] An[7:4] An[3:0]
M Size
Data Dn[3:0] Dn[7:4] 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address "An" in 7 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET XXXXb FWH4
Start FWH[3:0] 1101b
IDSEL 0000b
XXXXb XXXXb
XXA[17:16]b
Address
An[15:12] An[11:8] An[7:4] An[3:0]
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb Dn7,xxx 1111b
TAR Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
Read the DQ7 to see if the internal write complete or not.
CLK
#RESET
FWH4
Start FWH[3:0] 1101b
IDSEL 0000b
XXXXb XXXXb
XXA[17:16]b
Address
An[15:12] An[11:8] An[7:4] An[3:0]
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb Dn7,xxx 1111b
TAR Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
When internal write complete, the DQ7 will equal to Dn7.
- 24 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Toggle Bit Timing Diagram
CLK
#RESET
FWH4
Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb
XXA[17:16]b
Address
A[15:12] A[11:8] A[7:4] A[3:0]
M Size
Data D[3:0] D[7:4] 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address "An" in 7 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET
FWH4
Start FWH[3:0] 1101b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address XXXXb XXXXb XXXXb XXXXb
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb
X,D6,XXb
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
Read the DQ6 to see if the internal write complete or not.
CLK
#RESET
FWH4
Start FWH[3:0] 1101b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address XXXXb XXXXb XXXXb XXXXb
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb
X,D6,XXb
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock
Data out 2 Clocks
2 Clocks
1 Clock
When internal write complete, the DQ6 will stop toggle.
- 25 -
Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Boot Block Lockout Enable Timing Diagram
CLK
#RESET
FWH4
1st Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command Tri-State
2nd Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
Data 0101b 0101b 1111b
TAR Tri-State
Sync 0000b
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clocks
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command Tri-State
3rd Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 0000b 1000b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
4th Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command Tri-State
5th Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal program start 6th Start IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 0000b 0100b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State Internal program start
FWH[3:0] 1110b
0000b
1 Clock 1 Clock
Load Address "5555" 7 Clocks
Load Data "40" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Write the 6th command to the device in FWH mode.
- 26 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
FWH4 IDSEL 0000b
XXXXb XXXXb XXXXb
1st Start FWH[3:0] 1110b
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4 Data 0101b 0101b 1111b Start next command
2th Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4 Data 0000b 1000b TAR 1111b Tri-State Start next command
3th Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Sync 0000b 1111b
TAR Tri-State
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
FWH[3:0]
4th Start 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command
5th Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b 1111b
TAR Tri-State
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal erase start 6th Start IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 0000b 0001b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State Internal erase start
FWH[3:0] 1110b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "10" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Write the 6th command to the device in FWH mode.
- 27 -
Publication Release Date: February 19, 2002 Revision A2
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
Sector Erase Timing Diagram
CLK
#RESET
FWH4 Address
XXXXb XXXXb XXXXb
1st Start FWH[3:0] 1110b
IDSEL 0000b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
X101b
0101b
0101b
0101b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK #RESET
FWH4 Data 0101b 0101b 1111b Start next command
2nd Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK #RESET
FWH4 Data 0000b 1000b TAR 1111b Tri-State Start next command Tri-State
3rd Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Sync 0000b
TAR 1111b
0000b
1 Clocks1 Clocks
Load Address "5555" in 7 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clocks
2 Clocks
1 Clocks
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
FWH[3:0]
4th Start 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command Tri-State
5th Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal erase start 6th Start IDSEL 0000b
XXXXb XXXXb
XXA[17:16]b
Address
SA[15:12]
M Size
Data 0000b 0011b 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State Internal erase start
FWH[3:0] 1110b XXXXb XXXXb XXXXb 0000b
1 Clock 1 Clock
Load Sector Address in 7 Clocks
Load Din in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Write the 6th command(target sector to be erased) to the device in FWH mode.
- 28 -
W49V002FA
Timing Waveforms for FWH Interface Mode, continued
FGPI Register/Product ID Readout Timing Diagram
CLK
#RESET
FWH4
Start FWH[3:0] 1101b
IDSEL 0000b A[27:24] A[23:20] A[19:16]
Address 0000b 0001b /0000b 0000b 0000b /0001b
M Size
TAR 1111b
Sync 0000b D[3:0]
Data D[7:4]
TAR Tri-State 1111b
Next Start
0000b Tri-State
1 Clock 1 Clock
Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register & "FFBC0000(hex)/FFBC0001(hex) for Product ID
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins.
Reset Timing Diagram
VDD
TPRST
CLK TKRST #RESET TRST
F
TRSTP TRST
FWH[3:0]
FWH4
- 29 -
Publication Release Date: February 19, 2002 Revision A2
W49V002FA
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 11 11 POWER SUPPLY CURRENT MAX. (mA) 25 25 STANDBY VDD CURRENT MAX. (A) 20 20 PACKAGE
W49V002FAP W49V002FAQ
Notes:
32L PLCC 32L STSOP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
HOW TO READ THE TOP MARKING
Example: The top marking of 32L-PLCC W49V002FA
W49V002FAP 2123055C-082 132GHSA
st
1 line: winbond logo 2 line: the part number: W49V002FAP 3 line: the lot number 4 line: the tracking code: 132 G H SA 132: Packages made in '01, week 32 G: Assembly house ID: A means ASE, G means Greatek, ...etc. H: IC revision; A means version A, H means version H, ...etc. SA: Process code
th rd nd
- 30 -
W49V002FA
PACKAGE DIMENSIONS
32L PLCC
Dimension in Inches Dimension in mm
Symbol
HE E
Min. Nom. Max.
0.140 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 0 10
Min. Nom. Max.
3.56 0.50 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0 10
4
1
32
30
5
29
GD D HD
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
13
21
14
20
c
L A2 A
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc.
Seating Plane
e
b b1 GE
A1
y
32L STSOP (8 x 14 mm)
HD D c
Symbol Min. Nom. Max.
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.024 0.031 0.000 0 3 0.004 5 0.00 0 3 0.028 0.50 0.006 0.041 0.010 0.008 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.60 0.80 0.10 5 0.70
Dimension in Inches Dimension in mm Min. Nom. Max.
1.20 0.15 1.05 0.27 0.21
e
E
b
c
L L1
A1 A2 A
Y
A A1 A2 b c D E HD e L L1 Y
- 31 -
Publication Release Date: February 19, 2002 Revision A2
W49V002FA
VERSION HISTORY
VERSION A1 A2 DATE April 2001 Feb. 19, 2002 PAGE 4 6 7 - 10 13 Initial Issued Modify VDD Power Up/Down Detection in Hardware Data Protection Modify the description on start in TABLE OF COMMAND DEFINITION Delete old flow chart and add embedded algorithm Add in Input High Voltage for #INIT (VIHI) parameter Change VIL (max.) from 0.2 VDD to 0.3 VDD; VIH (min.) from 0.6 VDD to 0.5 VDD. Add the VIHI/ VILI for the #INIT pin input spec. 29 Add HOW TO READ THE TOP MARKING DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 32 -

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